1. Field of the Invention
The present invention relates to a relaxation oscillator circuit for generating a clock. In particular, the present invention relates to a relaxation oscillator circuit including two clock generator subcircuit.
2. Description of the Related Art
In recent years, due to the development of a number of micro systems such as implanted devices for use in medical applications and sensor devices, Large Scale Integrations (LSIs) are required to operate with a ultralow power. Therefore, a clock generator circuit to be mounted on an LSI is also required to operate with a low power, and is required to be on-chip mounted. A relaxation oscillator circuit is employed as a clock generator circuit that satisfies the above-described requirements. The relaxation oscillator circuit executes oscillating operation (referred to as a relaxation oscillating operation hereinafter) by charging and discharging a capacitor. However, the relaxation oscillator circuit has such a problem that a frequency (referred to as a clock frequency hereinafter) of a clock to be outputted therefrom fluctuates due to variations in the manufacturing processes of comparators for comparing a voltage across both terminals of the capacitor with a predetermined reference voltage. Concretely speaking, the clock frequency fluctuates, because an output signal from the comparator is delayed by a bias current of the comparator and a voltage level of the output signal from the comparator is not changed over at a desired timing due to an offset voltage of the comparator.
Prior art documents related to the present invention are listed below:
Non-Patent Document 1: K. Choe et al., “A Precision Relaxation Oscillator with a Self-Clocked Offset-Cancellation Scheme for Implantable Biomedical SoCs”, 2009 IEEE International Solid-State Circuits Conference (ISSCC), pp. 402-403, February, 2009;
Non-Patent Document 2: Y. Tokunaga et al., “An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback”, IEEE Journal of Solid-State Circuits, col. 45, No. 6, June 2010;
Non-Patent Document 3: “Flip-flop (electronics)”, [online], [searched on Aug. 16, 2011], Internet <URL: http://en.wikipedia.org/wiki/Flip-flop_(electronics)>; and
Non-Patent Document 4: K. Isono et al., “A PVT Variation Tolerant Clock Reference Circuit”, Proceedings of the Institute of Electronics, Information and Communication Engineers general conference, C-12-20, March, 2010.
A relaxation oscillator circuit described in the Non-Patent Document 1 suppresses the fluctuations in the clock frequency by correcting the offset voltage of the comparator. In addition, a relaxation oscillator circuit described in the Non-Patent Document 2 generates a comparison voltage for use in the comparator by comparing an input voltage to the comparator with a reference voltage by using an integrator circuit. This removes the influences of the delay and the offset voltage of the comparator on the clock frequency.
However, according to the Non-Patent Document 1, it was not possible to suppress the fluctuations in the clock frequency caused by the delay of the comparator. In addition, according to the Non-Patent Document 2, there is such a problem that the clock frequency fluctuates due to the offset voltage of an op-amp used in the integrator circuit since the integrator circuit is newly employed. Further, because it is required to use a resistor having a relatively high resistance value in the integrator circuit, the circuit area could not be reduced.